🎛️ Digital Input Controls (4 Data + 2 Select)
📁 Data Inputs (I0 – I3)
⚙️ Select Lines (S1, S0)
💡 Output & Selection Indicator
MANUAL MODE
Selected Input Channel
I0
Output Value (Y)
0
Multiplexer Output LED
LOGIC 0 (OFF)
⚡ 4:1 Multiplexer Gate-Level Schematic Diagram
Interactive Signal Animation & Wire Highlighting
🔍 Binary Data Demonstration & Gate Evaluation Panel
AND1 Output
I0 · S1̅ · S0̅
0
AND2 Output
I1 · S1̅ · S0
0
AND3 Output
I2 · S1 · S0̅
0
AND4 Output
I3 · S1 · S0
0
Select lines S1=0, S0=0 enable AND1 gate. Channel I0 is selected. Output Y = I0 = 0.
Boolean Equation: Y = I0·S1̅·S0̅ + I1·S1̅·S0 + I2·S1·S0̅ + I3·S1·S0
📊 Interactive Selection & Truth Table
Click any row to jump to select combination
| S1 | S0 | Selected Input | Active AND Gate | Output Equation | Current Output (Y) |
|---|---|---|---|---|---|
| 0 | 0 | I0 | AND1 (I0 · S1̅ · S0̅) | Y = I0 | 0 |
| 0 | 1 | I1 | AND2 (I1 · S1̅ · S0) | Y = I1 | 0 |
| 1 | 0 | I2 | AND3 (I2 · S1 · S0̅) | Y = I2 | 0 |
| 1 | 1 | I3 | AND4 (I3 · S1 · S0) | Y = I3 | 0 |
📚 Educational Theory & Engineering Applications
⚡ What is a 4:1 Multiplexer?
A Multiplexer (MUX), often called a Data Selector, is a combinational logic circuit designed to switch one of several input lines to a single common output line based on control signals.
A 4:1 Multiplexer features 4 Data Input lines (I0, I1, I2, I3), 2 Select Control lines (S1, S0), and 1 Output line (Y). The 2 select lines provide \(2^2 = 4\) distinct binary combinations, each enabling exactly one data channel to pass through to the output.
Y = (I0 · S1' · S0') + (I1 · S1' · S0) + (I2 · S1 · S0') + (I3 · S1 · S0)
🔬 Gate-Level Working Principle
The internal gate-level implementation uses 2 NOT gates to generate inverted select signals (\(\overline{S1}, \overline{S0}\)), 4 AND gates corresponding to each minterm combination, and 1 OR gate to merge the responses.
- S1=0, S0=0: Enables AND1 (\(I0 \cdot \overline{S1} \cdot \overline{S0}\)). Output \(Y = I0\).
- S1=0, S0=1: Enables AND2 (\(I1 \cdot \overline{S1} \cdot S0\)). Output \(Y = I1\).
- S1=1, S0=0: Enables AND3 (\(I2 \cdot S1 \cdot \overline{S0}\)). Output \(Y = I2\).
- S1=1, S0=1: Enables AND4 (\(I3 \cdot S1 \cdot S0\)). Output \(Y = I3\).
🚀 Real-World Engineering Applications
- Data Routing: Directs data streams from multiple sources to a shared bus or single transmission line.
- Digital Communication: Implements Time Division Multiplexing (TDM) to send multiple audio/data signals over a single channel.
- CPU & ALU Systems: Routes data between internal registers and the Arithmetic Logic Unit (ALU).
- Microprocessors: Selects address or data buses in memory management units (MMUs).
⚙️ Control & Acquisition Systems
- Data Acquisition Systems (DAS): Multiplexes sensor data (temperature, pressure, voltage) to a single Analog-to-Digital Converter (ADC).
- Signal Selection: Switches audio/video feeds in multimedia broadcast routing equipment.
- Control Systems: Selects control instructions based on active system operating states.
- Combinational Logic Generator: Used to synthesize arbitrary Boolean functions without additional gates.